1. Field of the Invention
This invention relates to methods of manufacturing semiconductor memory cells and more particularly to providing isolation between back-to-back MOSFET DRAM cells.
2. Description of Related Art
Present trends in Dynamic Random Access Memory (DRAM) technology are constantly driven towards reduction in minimum feature size xe2x80x9cFxe2x80x9d, where the value xe2x80x9cFxe2x80x9d represents the minimum feature structural dimension of the memory cell. Also the trends for DRAM devices are towards more compact cell layouts, i.e., denser than 8 F2, where the layout is the area required for a feature on the surface of the silicon substrate. Because of the need for ever increasing array densities, the scalability of contemporary planar metal oxide semiconductor field effect transistor (MOSFET) cells for smaller and smaller dimensions is facing fundamental concerns. The main concern with the scalability of the MOSFET cell is the increased P-well doping concentration needed to meet off-current objectives. It is well known in the art that increased array well doping concentration may result in a marked increase in array junction leakage, which degrades retention time. The problem of scalability related to the MOSFET cell, by itself, is driving the paradigm shift towards vertical MOSFET access transistors in the array.
There is a need for DRAM cells containing vertical access transistors with dense layouts and trench storage capacitors which yield sufficient capacitance and reduced series resistance to avoid degraded signal development.
Although some existing DRAM cells employing vertical MOSFETs offer very significant scalability advantages over conventional planar designs practiced today, there is still a great deal of room for improvement. For example, for cells using vertical MOSFETs and trench storage capacitors, a single bitline contact is commonly used to access a pair of bits; the pair of bits share a common silicon Active Area (AA). In this type of cell, dynamic coupling between the two back-to-back vertical MOSFETs results in charge pumping effects and loss of signal. Modeling has shown that electrons pumped into the P-well from a collapsing channel inversion layer of one cell may be collected by the storage node of the adjacent cell sharing the same AA. These coupling effects are accentuated as dimensions are scaled down. Modeling projections indicate that scalability to smaller and smaller dimensions will be problematic because of dynamic charge loss due to coupling between adjacent cell.
In addition to charge pumping problems, very dense prior art designs suffer from threshold voltage variations in the size of the silicon AA which occurs with overlay (alignment) errors between various masking levels and with dimensional variations of features formed by these masking levels.
Another problem faced with aggressively scaled DRAM cells is the increased aspect ratio (height to width) of the isolation regions. This is especially a concern with vertical MOSFETs in the array because of the requirement that the isolation trench be deep enough to cut the outdiffusion strap so as to prevent cell-to-cell leakage between straps. Typically, it is required that the isolation trench be at least 500 nm in depth to isolate the outdiffusion straps of the vertical MOSFETs. If the thickness of the pad layer is included, an isolation trench aspect ratio of 7:1 is anticipated by the 100 nm generation.
In view of the drawbacks mentioned hereinabove with prior art DRAM cell designs, there is a continued need to develop new and improved DRAM cell designs that are denser than prior art designs and have a larger DT size. A larger DT size is advantageous in dense DRAM cells since it provides a large storage capacitance and reduced series resistance to the array cell.
As indicated above, scaling of vertical MOSFET DRAM cells is limited by loss of data caused by dynamic coupling between back-to-back cells. For the existing structure and process, this mechanism may prevent the successful scaling of the 8 F2 vertical MOSFET DRAM to 90 nm ground rules, where the value xe2x80x9cFxe2x80x9d represents the minimum feature size of the device, i.e. the dimension xe2x80x9cFxe2x80x9d is the minimum structural dimension of the memory cell.
U.S. Pat. No. 6,018,174 of Schrems et al. for xe2x80x9cBottle-Shaped Trench Capacitor with Epi Buried Layerxe2x80x9d describes a bottle-shaped trench capacitor with an expanded lower trench portion and an epitaxial layer that is the buried plate of the trench capacitor. The patent states that xe2x80x9cA conventional technique for forming the buried plate includes outdiffusing dopants into the substrate region surrounding the lower portion of the trench. One type of capacitor that is commonly employed in DRAMs is the trench capacitor. A trench capacitor is a three-dimensional structure formed in the substrate. Typically, a trench capacitor comprises a deep trench etched into the substrate. The trench is filled, for example, with n-type doped poly. The doped poly serves as one electrode of the capacitor (referred to as the xe2x80x9cstorage nodexe2x80x9d). An n-type doped region surrounds the lower portion of the trench, serving as a second electrode. The doped region is referred to as a xe2x80x9cburied plate.xe2x80x9d A node dielectric separates the buried plate and the storage node.
U.S. Pat. No. 6,163,045 Mandelman et al. for xe2x80x9cReduced Parasitic Leakage in Semiconductor Devicesxe2x80x9d describes a trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET enabling the use of a thinner collar while still achieving an acceptable level of leakage. The patent states that xe2x80x9cTrench capacitors are commonly employed in DRAMs. A trench capacitor is a three-dimensional structure formed into the silicon substrate. A conventional trench capacitor comprises a trench etched into the substrate. The trench is typically filled with n+ doped poly which serves as one plate of the capacitor (referred to as the storage node). The second plate of the capacitor, referred to as a xe2x80x98buried plate,xe2x80x99 is formed by, for example, outdiffusing n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A dielectric layer is provided to separate the two plates forming the capacitor. To prevent or reduce parasitic leakage that occurs along the upper portion of the trench to an acceptable level, an oxide collar of sufficient thickness is provided therein.xe2x80x9d The patent states further that xe2x80x9cp-type dopants, such as boron (B) are implanted into the well region. The dopants are implanted sufficiently deep to prevent punchthrough and to reduce sheet resistance. The dopant profile is tailored to achieve the desired electrical characteristics, e.g., gate threshold voltage (VT)xe2x80x9d. The device includes an arrangement referred to here as Bilateral BSOD (BBSOD) configuration, i.e. there are buried strap outdiffusion regions on both sides of the deep trench of the device, but it should be noted that there is only one isolated deep trench device shown in the device, so there is no showing of BSOD regions in a confrontational configuration in a P-well.
Commonly assigned U.S. Pat. No. 6,281,539 of Mandelman et al. for xe2x80x9cStructure and Process for 6 F2 DT Cell Having Vertical MOSFET and Large Storage Capacitancexe2x80x9d describes a 6 F2 memory cell comprising a plurality of capacitors each located in a separate trench that is formed in a semiconductor substrate. Each of a plurality of transfer transistors has a vertical gate dielectric, a gate conductor, and a bitline diffusion, and each transistor is located above and electrically connected to a respective trench capacitor. About the transistors are dielectric-filled isolation trenches spaced apart by a substantially uniform spacing in a striped pattern. A respective wordline is electrically contacted to each respective gate conductor.
The above Mandelman et al. U.S. Pat. No. 6,281,539 states as follows xe2x80x9cTo prevent unwanted formation of strap diffusion on the side of the trench which is adjacent to the oxide fill, a thin Si3N4 barrier layer (i.e., about 1 nm or less) may be formed prior to the deposition of the strap polysilicon. For simplicity, this barrier layer is not shown in the drawings of the present invention. The barrier nitride impedes the diffusion of dopant from the N+ DT poly into the substrate during gate oxidation. Later thermal processing breaks down this barrier layer, allowing the strap to outdiffuse on the desired side of the trench. Other options that may be employed in the present invention to impede unwanted strap outdiffusion include, but are not limited to: low temperature gate oxidation and isotropic etching of a small amount of substrate on the trench sidewall.xe2x80x9d
Commonly assigned U.S. Pat. No. 6,284,593 of Mandelman et al. for xe2x80x9cMethod for Shallow Trench Isolated, Contacted Well, Vertical MOSFET DRAMxe2x80x9d describes a floating-well dynamic leakage mechanism that limits scalability of vertical DRAM memory arrays. Specifically, during a long period of about 5-100 ns of repeated writing of a xe2x80x9c1xe2x80x9d to other memory cells on the bitline, the P-well of an unselected cell storing a xe2x80x9c1xe2x80x9d may suffer from leakage, as the exiting of holes is restricted by a parasitic JFET. The patent states that xe2x80x9cLeakage depends on the degree of well isolation caused by pinchoff from expansion of the storage node depletion region. In an extreme case, the buried-strap region may come in contact with the adjacent deep trench capacitor. Moreover, the hole current through the pinchoff region must keep up with the leakage to avoid a pseudo xe2x80x98Floating-Body Effectxe2x80x99xe2x80x9d.
The above Mandelman et al. U.S. Pat. No. 6,284,593 states further that xe2x80x9cFor aggressively scaled metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM memory cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in xe2x80x98Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)xe2x80x99, Proceeding, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, October 1996.xe2x80x9d
Commonly assigned U.S. Pat. No. 6,440,872 of Mandelan et al. for xe2x80x9cMethod for Hybrid DRAM Cell Utilizing Confined Strap Isolationxe2x80x9d which has a similar description to U.S. Pat. No. 6,284,593 describes forming a planarized layer of oxide in etched arms on an oxide/nitride liner so as to form shallow isolation trench regions which have a depth that is substantially above a buried-strap outdiffusion region to be subsequently for thereby not cutting into a BSOD region, yet being deep enough for isolation of adjacent bitline diffusion regions that are subsequently formed, but it does not relate to isolation of outdiffusion regions.
Commonly assigned U.S. Pat. No. 6,441,422 of Mandelman et al. for xe2x80x9cStructure and Method for Ultra-scalable Hybrid DRAM Cell with Contacted P-Wellxe2x80x9d is similar to U.S. Pat. Nos. 6,440,872 and 6,284,593 discussed above.
Commonly assigned U.S. Pat. No. 6,440,793 Divakaruni et al. for xe2x80x9cVertical MOSFETxe2x80x9d describes a process for making a vertical MOSFET DRAM cell array with a deposited gate conductor layer planarized to a top surface of a trench top oxide and a silicon substrate. Then form a recess in the gate conductor layer below the top surface of the silicon substrate. Next, angle implant N-type dopant through the recess to form doping pockets in an array P-well. An oxide layer is deposited into the recess. The oxide layer is etched to form spacers on sidewalls of the recess. A gate conductor material is deposited into the recess and the gate conductor is planarized to the top surface of the trench top oxide. There is a unilateral BSOD, i.e. there is a strap on only one side of the deep trench.
All of the above patents include unilateral Buried Strap OutDiffusions (BSOD""s), i.e. there is a strap on only one side of the deep trenches shown. We have discovered these shortcomings and decided to pursue the bilateral (8 F2) cell approach because the design with the unilateral (single) strap suffers from a host of scalability problems, which are different from and more severe than the scalability problems of the cell with the bilateral straps.
An object of this invention is to provide an improved way to suppress the loss of a stored xe2x80x9c1xe2x80x9d due to the dynamic loss mechanism, as described above.
It is a further object of this invention to provide a simple, cost effective, method for forming the improved structure, thereby significantly extending the scalability of 8 F2 vertical MOSFET DRAM arrays.
In summary, the present invention provides the following advantages over the existing art:
1. Allows scaling of 8 F2 vertical MOSFET DRAM cells to 90 nm and beyond;
2. Allows reduction in array P-well doping concentration adjacent to back-to-back cells (i.e. Confronting Buried Strap OutDiffusions (BSOD""s)), for reduced junction leakage and improved retention time.
In accordance with the method of the present invention, a structure is formed which has significantly improved immunity to cell-to-cell interaction.
Further in accordance with the method of this present invention, a locally enhanced P-well doping region is formed between back-to-back cells, without significantly affecting the doping concentration at the strap diffusion junctions.
Moreover, the method of this invention contains the localized doping concentration to the mid-region between back-to-back cell sites, without significantly affecting the Vt of the vertical MOSFETs, and without degrading the substrate sensitivity.
Additionally the method of this invention can be readily integrated into an existing process at minimal cost.
In accordance with this invention, a method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate; with outdiffusion strap regions (which can be bilateral) formed extending from the trenches into a doped semiconductor region and with adjacent deep trenches having confronting pairs of outdiffusion regions extending from adjacent deep trenches into the doped semiconductor region. The method includes the step of forming an isolation diffusion region in the substrate between the back-to-back cells separating the confronting outdiffusion strap regions so that the fields surrounding the outdiffusion/strap regions are separated by the isolation diffusion region.
Preferably, before forming the isolation diffusion region, the steps are performed of forming an isolation trench masking layer with openings between rows of deep trenches, and then etching through the openings in the isolation trench masking layer to form isolation trenches between rows of deep trenches.
Preferably, before forming the isolation diffusion region, the step is performed of forming a parallel array of active area liners composed of silicon oxide, followed by depositing a conformal first silicon nitride liner on the sidewalls of the isolation trenches thereby narrowing the isolation trenches and above other surfaces of the structure.
Preferably, before forming the isolation diffusion region, the steps are performed of filling the isolation trenches with sacrificial silicon oxide, planarizing the sacrificial silicon oxide, and forming a blanket silicon nitride layer over the structure forming a silicon oxide masking layer over the blanket silicon nitride layer, and etching a parallel array of shallow trenches through the silicon oxide masking layer, thereby forming silicon oxide stripes orthogonal to the active area stripes by etching through the silicon oxide masking layer.
Preferably, before forming the isolation diffusion region the step is performed of doping the diffusion isolation regions between the deep trenches.
Preferably, before forming the isolation diffusion region, the steps are performed of forming spacers on the sidewalls of the parallel array of shallow trenches thereby forming narrowed shallow trenches, forming windows to a diffusion isolation regions in the substrate and to the gate conductors and by etching through the narrowed shallow trenches, stripping the silicon oxide masking layer and the spacers, and doping the diffusion isolation regions through the widows.
Preferably, before forming the isolation diffusion region, the steps are performed of forming a blanket silicon nitride protective layer and forming a planarized silicon oxide layer thereover.
In accordance with another aspect of this invention, a method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells formed in a planar semiconductor substrate with a doped plate region in the substrate below a counterdoped well region, deep trenches formed therein extending into the substrate through the well region and into the plate region. Each deep trench has side walls and a bottom with bilateral outdiffusion strap regions which extend from the deep trenches, located in the well region midway up the sidewalls of the deep trenches. The outdiffusion strap regions and a plate region formed in the substrate from lower levels of the deep trench to below the deep trenches. A collar is formed along middle levels of the sidewalls of the deep trench from a lower portion of the strap regions down towards the plate region of the substrate and a node dielectric covering lower sidewalls and the bottom of the deep trenches. The deep trenches have capacitor nodes formed in the bottoms thereof. Trench top dielectric layers are formed above the capacitor nodes. A gate oxide layer is formed on the sidewalls of the deep trench above the capacitor nodes and a gate conductor is formed above the trench top dielectric layer and inside the gate oxide layer in the deep trenches. The memory structure is made by including the step of forming an isolation diffusion region in the substrate between the back-to-back cells separating the confronting the outdiffusion strap regions so that the fields surrounding the outdiffusion/strap regions are separated by the isolation diffusion region.